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![courses:system_design:synthesis:master-slave_flip-flop:rs-ff [VHDL-Online]](https://www.vhdl-online.de/_media/courses/system_design/synthesis/master-slave_flip-flop/folie320_rsffcircuit.svg?w=500&tok=bf65ae "courses:system_design:synthesis:master-slave_flip-flop:rs-ff [VHDL-Online]")
courses:system_design:synthesis:master-slave_flip-flop:rs-ff [VHDL-Online]
Master-slave JK-flipflop with reset
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